Index: dev/mii/brgphy.c
===================================================================
RCS file: /cvs/src/sys/dev/mii/brgphy.c,v
retrieving revision 1.15
diff -u -r1.15 brgphy.c
--- dev/mii/brgphy.c	13 Oct 2003 16:18:56 -0000	1.15
+++ dev/mii/brgphy.c	5 Sep 2005 14:31:22 -0000
@@ -1,4 +1,4 @@
-/*	$OpenBSD: brgphy.c,v 1.15 2003/10/13 16:18:56 krw Exp $	*/
+/*	$OpenBSD: brgphy.c,v 1.18 2004/10/31 06:59:25 brad Exp $	*/
 
 /*
  * Copyright (c) 2000
@@ -100,7 +100,8 @@
 	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701 ||
 	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703 ||
 	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704 ||
-	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705))
+	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705 ||
+	     MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750))
 		return(10);
 
 	return(0);
@@ -133,6 +134,8 @@
 		model = MII_STR_xxBROADCOM_BCM5704;
 	if (MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705)
 		model = MII_STR_xxBROADCOM_BCM5705;
+	if (MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750)
+		model = MII_STR_xxBROADCOM_BCM5750;
 
 	printf(": %s, rev. %d\n", model, MII_REV(ma->mii_id2));
 
@@ -242,23 +245,6 @@
 
 			if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
  				break;
-
-			/*
-			 * On IFM_1000_X only,
-			 * when setting the link manually, one side must
-			 * be the master and the other the slave. However
-			 * ifmedia doesn't give us a good way to specify
-			 * this, so we fake it by using one of the LINK
-			 * flags. If LINK0 is set, we program the PHY to
-			 * be a master, otherwise it's a slave.
-			 */
-			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
-				PHY_WRITE(sc, BRGPHY_MII_1000CTL,
-				    gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
-			} else {
-				PHY_WRITE(sc, BRGPHY_MII_1000CTL,
-				    gig|BRGPHY_1000CTL_MSE);
-			}
 			break;
 		default:
 			return (EINVAL);
@@ -511,6 +497,18 @@
 	{ 0,				0 },
 };
 
+static const struct bcm_dspcode bcm5750_dspcode[] = {
+	{ 0x18,				0x0c00 },
+	{ 0x17,				0x000a },
+	{ 0x15,				0x310b },
+	{ 0x17,				0x201f },
+	{ 0x15,				0x9506 },
+	{ 0x17,				0x401f },
+	{ 0x15,				0x14e2 },
+	{ 0x18,				0x0400 },
+	{ 0,				0 },
+};
+
 void
 brgphy_load_dspcode(sc)
 	struct mii_softc *sc;
@@ -537,6 +535,9 @@
 		break;
 	case MII_MODEL_xxBROADCOM_BCM5704:
 		dsp = bcm5704_dspcode;
+		break;
+	case MII_MODEL_xxBROADCOM_BCM5750:
+		dsp = bcm5750_dspcode;
 		break;
 	}
 
Index: dev/mii/miidevs.h
===================================================================
RCS file: /cvs/src/sys/dev/mii/miidevs.h,v
retrieving revision 1.46
diff -u -r1.46 miidevs.h
--- dev/mii/miidevs.h	10 Aug 2004 04:32:58 -0000	1.46
+++ dev/mii/miidevs.h	5 Sep 2005 14:31:23 -0000
@@ -1,10 +1,10 @@
-/*	$OpenBSD: miidevs.h,v 1.46 2004/08/10 04:32:58 brad Exp $	*/
+/*	$OpenBSD: miidevs.h,v 1.47 2004/10/01 19:07:49 brad Exp $	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	OpenBSD: miidevs,v 1.43 2004/08/10 04:31:12 brad Exp 
+ *	OpenBSD: miidevs,v 1.44 2004/10/01 19:05:19 brad Exp 
  */
 /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
 
@@ -136,6 +136,8 @@
 #define	MII_STR_xxBROADCOM_BCM5704	"BCM5704 10/100/1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5705	0x001a
 #define	MII_STR_xxBROADCOM_BCM5705	"BCM5705 10/100/1000baseT PHY"
+#define	MII_MODEL_xxBROADCOM_BCM5750	0x0018
+#define	MII_STR_xxBROADCOM_BCM5750	"BCM5750 10/100/1000baseT PHY"
 #define	MII_MODEL_BROADCOM_BCM5400	0x0004
 #define	MII_STR_BROADCOM_BCM5400	"BCM5400 1000baseT PHY"
 #define	MII_MODEL_BROADCOM_BCM5401	0x0005
Index: dev/mii/miidevs
===================================================================
RCS file: /cvs/src/sys/dev/mii/miidevs,v
retrieving revision 1.43
diff -u -r1.43 miidevs
--- dev/mii/miidevs	10 Aug 2004 04:31:12 -0000	1.43
+++ dev/mii/miidevs	5 Sep 2005 14:31:24 -0000
@@ -1,4 +1,4 @@
-$OpenBSD: miidevs,v 1.43 2004/08/10 04:31:12 brad Exp $
+$OpenBSD: miidevs,v 1.44 2004/10/01 19:05:19 brad Exp $
 /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
 
 /*-
@@ -116,6 +116,7 @@
 model xxBROADCOM BCM5703	0x0016 BCM5703 10/100/1000baseT PHY
 model xxBROADCOM BCM5704	0x0019 BCM5704 10/100/1000baseT PHY
 model xxBROADCOM BCM5705	0x001a BCM5705 10/100/1000baseT PHY
+model xxBROADCOM BCM5750	0x0018 BCM5750 10/100/1000baseT PHY
 model BROADCOM BCM5400		0x0004 BCM5400 1000baseT PHY
 model BROADCOM BCM5401		0x0005 BCM5401 1000baseT PHY
 model BROADCOM BCM5411		0x0007 BCM5411 1000baseT PHY
Index: dev/pci/if_bge.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_bge.c,v
retrieving revision 1.30
diff -u -r1.30 if_bge.c
--- dev/pci/if_bge.c	19 Aug 2004 17:00:03 -0000	1.30
+++ dev/pci/if_bge.c	5 Sep 2005 14:31:26 -0000
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bge.c,v 1.30 2004/08/19 17:00:03 mcbride Exp $	*/
+/*	$OpenBSD: if_bge.c,v 1.34 2004/10/31 06:59:25 brad Exp $	*/
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -212,8 +212,12 @@
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705 },
+	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT },
+	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750 },
+	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M },
+	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751 },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782 },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788 },
 	{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901 },
@@ -1016,7 +1020,11 @@
 		BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
 
 	/* Set up the PCI DMA control register. */
-	if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
+	if (sc->bge_pcie) {
+		dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
+		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
+		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+	} else if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
 	    BGE_PCISTATE_PCI_BUSMODE) {
 		/* Conventional PCI bus */
 		dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
@@ -1055,7 +1063,8 @@
  
 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 	    sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
-	    sc->bge_asicrev == BGE_ASICREV_BCM5705)
+	    sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
 
 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
@@ -1116,7 +1125,8 @@
 
 	/* Note: the BCM5704 has a smaller bmuf space than the other chips */
 
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		/* Configure mbuf memory pool */
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
 		    (sc->bge_extram) ? BGE_EXT_SSRAM : BGE_BUFFPOOL_1);
@@ -1130,7 +1140,8 @@
 	}
 
 	/* Configure mbuf pool watermarks */
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+	    sc->bge_asicrev == BGE_ASICREV_BCM5750) {
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
 	} else {
@@ -1144,7 +1155,8 @@
 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 
 	/* Enable buffer manager */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		CSR_WRITE_4(sc, BGE_BMAN_MODE,
 		    BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
 
@@ -1182,7 +1194,8 @@
 	/* Initialize the standard RX ring control block */
 	rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
 	BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
 	else
 		rcb->bge_maxlen_flags =
@@ -1203,7 +1216,8 @@
 	 * using this ring (i.e. once we set the MTU
 	 * high enough to require it).
 	 */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 		BGE_HOSTADDR(rcb->bge_hostaddr,
 		    BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
@@ -1260,7 +1274,8 @@
 		    BGE_RING_DMA_ADDR(sc, bge_tx_ring));
 	RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
 		    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
 
@@ -1344,7 +1359,8 @@
 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
 	}
@@ -1352,7 +1368,8 @@
 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
 
 	/* Set up address of statistics block */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
 			    BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
@@ -1381,7 +1398,8 @@
 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 
 	/* Turn on RX list selector state machine. */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 
 	/* Turn on DMA, clear stats */
@@ -1403,7 +1421,8 @@
 #endif
 
 	/* Turn on DMA completion state machine */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 
 	/* Turn on write DMA state machine */
@@ -1424,7 +1443,8 @@
 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
 
 	/* Turn on Mbuf cluster free state machine */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 
 	/* Turn on send BD completion state machine */
@@ -1563,6 +1583,29 @@
 	}
 	printf(": %s", intrstr);
 
+	/* Save ASIC rev. */
+
+	sc->bge_chipid =
+            pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
+            BGE_PCIMISCCTL_ASICREV;
+        sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
+        sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
+
+	/*
+	 * XXX: Broadcom Linux driver.  Not in specs or eratta.
+	 * PCI-Express?
+	 */
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
+		u_int32_t v;
+
+		v = pci_conf_read(pc, pa->pa_tag, BGE_PCI_MSI_CAPID);
+		if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
+			v = pci_conf_read(pc, pa->pa_tag, BGE_PCIE_CAPID_REG);
+			if ((v & 0xff) == BGE_PCIE_CAPID)
+				sc->bge_pcie = 1;
+		}
+	}
+
 	/* Try to reset the chip. */
 	DPRINTFN(5, ("bge_reset\n"));
 	bge_reset(sc);
@@ -1644,19 +1687,12 @@
 
 	bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
 
-	/* Save ASIC rev. */
-
-	sc->bge_chipid =
-	    pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
-	    BGE_PCIMISCCTL_ASICREV;
-	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
-	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
-
 	/*
 	 * Try to allocate memory for jumbo buffers.
 	 * The 5705 does not appear to support jumbo frames.
 	 */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		if (bge_alloc_jumbo_mem(sc)) {
 			printf("%s: jumbo buffer allocation failed\n",
 			    sc->bge_dev.dv_xname);
@@ -1673,7 +1709,8 @@
 	sc->bge_tx_max_coal_bds = 128;
 
 	/* 5705 limits RX return ring to 512 entries. */
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
 	else
 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
@@ -1820,7 +1857,7 @@
 	struct bge_softc *sc;
 {
 	struct pci_attach_args *pa = &sc->bge_pa;
-	u_int32_t cachesize, command, pcistate;
+	u_int32_t cachesize, command, pcistate, reset;
 	int i, val = 0;
 
 	/* Save some important PCI state. */
@@ -1832,12 +1869,37 @@
 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
 	    BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
 
+	reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
+
+	/* XXX: Broadcom Linux driver. */
+	if (sc->bge_pcie) {
+		if (CSR_READ_4(sc, 0x7e2c) == 0x60)	/* PCIE 1.0 */
+			CSR_WRITE_4(sc, 0x7e2c, 0x20);
+		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
+			/* Prevent PCIE link training during global reset */
+			CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
+			reset |= (1<<29);
+		}
+	}
+
 	/* Issue global reset */
-	bge_writereg_ind(sc, BGE_MISC_CFG,
-	    BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
+	bge_writereg_ind(sc, BGE_MISC_CFG, reset);
 
 	DELAY(1000);
 
+	/* XXX: Broadcom Linux driver. */
+	if (sc->bge_pcie) {
+		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
+			uint32_t v;
+
+			DELAY(500000); /* wait for link training to complete */
+			v = pci_conf_read(pa->pa_pc, pa->pa_tag, 0xc4);
+			pci_conf_write(pa->pa_pc, pa->pa_tag, 0xc4, v | (1<<15));
+		}
+		/* Set PCIE max payload size and clear error status. */
+		pci_conf_write(pa->pa_pc, pa->pa_tag, 0xd8, 0xf5000);
+	}
+
 	/* Reset some of the PCI state that got zapped by reset */
 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
@@ -1847,7 +1909,8 @@
 	bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
 
 	/* Enable memory arbiter. */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 
 	/*
@@ -1895,6 +1958,12 @@
 
 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 
+	/* XXX: Broadcom Linux driver. */
+	if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
+		uint32_t v;
+		v = CSR_READ_4(sc, 0x7c00);
+		CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
+	}
 	DELAY(10000);
 }
 
@@ -2187,7 +2256,8 @@
 
 	s = splimp();
 
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
 		bge_stats_update_regs(sc);
 	else
 		bge_stats_update(sc);
@@ -2673,7 +2743,8 @@
 		break;
 	case SIOCSIFMTU:
 		/* Disallow jumbo frames on 5705. */
-		if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
+		if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
+		      sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
 		    ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > ETHERMTU_JUMBO)
 			error = EINVAL;
 		else
@@ -2780,7 +2851,8 @@
 	BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
@@ -2794,7 +2866,8 @@
 	BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 
@@ -2804,11 +2877,13 @@
 	 */
 	BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 	}
@@ -2826,7 +2901,8 @@
 	bge_free_rx_ring_std(sc);
 
 	/* Free jumbo RX list. */
-	if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
+	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 		bge_free_rx_ring_jumbo(sc);
 
 	/* Free TX buffers. */
Index: dev/pci/if_bgereg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_bgereg.h,v
retrieving revision 1.10
diff -u -r1.10 if_bgereg.h
--- dev/pci/if_bgereg.h	5 Aug 2004 19:57:17 -0000	1.10
+++ dev/pci/if_bgereg.h	5 Sep 2005 14:31:28 -0000
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.10 2004/08/05 19:57:17 brad Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.12 2004/10/31 06:59:25 brad Exp $ */
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -170,6 +170,10 @@
 #define BGE_PCI_MSI_ADDR_LO		0x60
 #define BGE_PCI_MSI_DATA		0x64
 
+/* PCI MSI. ??? */
+#define BGE_PCIE_CAPID_REG		0xD0
+#define BGE_PCIE_CAPID			0x10
+
 /*
  * PCI registers specific to the BCM570x family.
  */
@@ -235,6 +239,8 @@
 #define BGE_CHIPID_BCM5705_A1		0x30010000
 #define BGE_CHIPID_BCM5705_A2		0x30020000
 #define BGE_CHIPID_BCM5705_A3		0x30030000
+#define BGE_CHIPID_BCM5750_A0		0x40000000
+#define BGE_CHIPID_BCM5750_A1		0x40010000
 
 /* shorthand one */
 #define BGE_ASICREV(x)			((x) >> 28)
@@ -243,6 +249,7 @@
 #define BGE_ASICREV_BCM5703		0x01
 #define BGE_ASICREV_BCM5704		0x02
 #define BGE_ASICREV_BCM5705		0x03
+#define BGE_ASICREV_BCM5750		0x04
 
 /* chip revisions */
 #define BGE_CHIPREV(x)			((x) >> 24)
@@ -2200,6 +2207,7 @@
 	u_int8_t		bge_asicrev;
 	u_int8_t		bge_chiprev;
 	u_int8_t		bge_no_3_led;
+	u_int8_t		bge_pcie;
 	struct bge_ring_data	*bge_rdata;	/* rings */
 	struct bge_chain_data	bge_cdata;	/* mbufs */
 	bus_dmamap_t		bge_ring_map;
Index: dev/pci/pcidevs.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.762
diff -u -r1.762 pcidevs.h
--- dev/pci/pcidevs.h	6 Sep 2004 08:48:02 -0000	1.762
+++ dev/pci/pcidevs.h	5 Sep 2005 14:31:32 -0000
@@ -742,8 +742,12 @@
 #define	PCI_PRODUCT_BROADCOM_BCM5704C	0x1648		/* BCM5704C */
 #define	PCI_PRODUCT_BROADCOM_BCM5702FE	0x164d		/* BCM5702FE */
 #define	PCI_PRODUCT_BROADCOM_BCM5705	0x1653		/* BCM5705 */
+#define	PCI_PRODUCT_BROADCOM_BCM5705K	0x1654		/* BCM5705K */
 #define	PCI_PRODUCT_BROADCOM_BCM5705M	0x165d		/* BCM5705M */
 #define	PCI_PRODUCT_BROADCOM_BCM5705M_ALT	0x165e		/* BCM5705M_ALT */
+#define	PCI_PRODUCT_BROADCOM_BCM5750	0x1676		/* BCM5750 */
+#define	PCI_PRODUCT_BROADCOM_BCM5750M	0x167c		/* BCM5750M */
+#define	PCI_PRODUCT_BROADCOM_BCM5751	0x1677		/* BCM5751 */
 #define	PCI_PRODUCT_BROADCOM_BCM5782	0x1696		/* BCM5782 */
 #define	PCI_PRODUCT_BROADCOM_BCM5788	0x169c		/* BCM5788 */
 #define	PCI_PRODUCT_BROADCOM_BCM5702X	0x16a6		/* BCM5702X */
@@ -1095,6 +1099,10 @@
 #define	PCI_PRODUCT_HP_NETRAID_4M	0x10c2		/* NetRaid-4M */
 #define	PCI_PRODUCT_HP_SMARTIRQ	0x10ed		/* NetServer SmartIRQ */
 #define	PCI_PRODUCT_HP_82557B	0x1200		/* 82557B 10/100 NIC */
+#define	PCI_PRODUCT_HP_PLUTO	0x1229		/* Pluto MIO */
+#define	PCI_PRODUCT_HP_ZX1_IOC	0x122a		/* zx1 IOC */
+#define	PCI_PRODUCT_HP_MERCURY	0x122e		/* Mercury Ropes-PCI */
+#define	PCI_PRODUCT_HP_QUICKSILVER	0x12b4		/* QuickSilver Ropes-PCI */
 
 /* Hifn products */
 #define	PCI_PRODUCT_HIFN_7751	0x0005		/* 7751 */
Index: dev/pci/pcidevs
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.758
diff -u -r1.758 pcidevs
--- dev/pci/pcidevs	6 Sep 2004 08:46:26 -0000	1.758
+++ dev/pci/pcidevs	5 Sep 2005 14:31:34 -0000
@@ -1,4 +1,4 @@
-$OpenBSD: pcidevs,v 1.758 2004/09/06 08:46:26 markus Exp $
+$OpenBSD: pcidevs,v 1.775 2004/10/02 00:23:57 brad Exp $
 /*	$NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ 	*/
 
 /*
@@ -737,8 +737,12 @@
 product BROADCOM BCM5704C	0x1648	BCM5704C
 product BROADCOM BCM5702FE	0x164d	BCM5702FE
 product BROADCOM BCM5705	0x1653	BCM5705
+product BROADCOM BCM5705K	0x1654	BCM5705K
 product BROADCOM BCM5705M	0x165d	BCM5705M
 product BROADCOM BCM5705M_ALT	0x165e	BCM5705M_ALT
+product BROADCOM BCM5750	0x1676	BCM5750
+product BROADCOM BCM5750M	0x167c	BCM5750M
+product BROADCOM BCM5751	0x1677	BCM5751
 product BROADCOM BCM5782	0x1696	BCM5782
 product BROADCOM BCM5788	0x169c	BCM5788
 product BROADCOM BCM5702X	0x16a6	BCM5702X
@@ -1090,6 +1094,10 @@
 product HP NETRAID_4M		0x10c2	NetRaid-4M
 product HP SMARTIRQ		0x10ed	NetServer SmartIRQ
 product HP 82557B		0x1200	82557B 10/100 NIC
+product HP PLUTO		0x1229	Pluto MIO
+product HP ZX1_IOC		0x122a	zx1 IOC
+product HP MERCURY		0x122e	Mercury Ropes-PCI
+product HP QUICKSILVER		0x12b4	QuickSilver Ropes-PCI
 
 /* Hifn products */
 product HIFN 7751		0x0005	7751
Index: dev/pci/pcidevs_data.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.762
diff -u -r1.762 pcidevs_data.h
--- dev/pci/pcidevs_data.h	6 Sep 2004 08:48:02 -0000	1.762
+++ dev/pci/pcidevs_data.h	5 Sep 2005 14:31:38 -0000
@@ -1603,6 +1603,10 @@
 	    "BCM5705",
 	},
 	{
+	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
+	    "BCM5705K",
+	},
+	{
 	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 	    "BCM5705M",
 	},
@@ -1611,6 +1615,18 @@
 	    "BCM5705M_ALT",
 	},
 	{
+	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
+	    "BCM5750",
+	},
+	{
+	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
+	    "BCM5750M",
+	},
+	{
+	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
+	    "BCM5751",
+	},
+	{
 	    PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 	    "BCM5782",
 	},
@@ -2641,6 +2657,22 @@
 	{
 	    PCI_VENDOR_HP, PCI_PRODUCT_HP_82557B,
 	    "82557B 10/100 NIC",
+	},
+	{
+	    PCI_VENDOR_HP, PCI_PRODUCT_HP_PLUTO,
+	    "Pluto MIO",
+	},
+	{
+	    PCI_VENDOR_HP, PCI_PRODUCT_HP_ZX1_IOC,
+	    "zx1 IOC",
+	},
+	{
+	    PCI_VENDOR_HP, PCI_PRODUCT_HP_MERCURY,
+	    "Mercury Ropes-PCI",
+	},
+	{
+	    PCI_VENDOR_HP, PCI_PRODUCT_HP_QUICKSILVER,
+	    "QuickSilver Ropes-PCI",
 	},
 	{
 	    PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751,