Index: arch/i386/i386/apm.c
===================================================================
RCS file: /u/open/cvs/src/sys/arch/i386/i386/apm.c,v
retrieving revision 1.58
diff -u -r1.58 apm.c
--- arch/i386/i386/apm.c	29 Jan 2003 00:00:44 -0000	1.58
+++ arch/i386/i386/apm.c	23 Jun 2004 17:02:31 -0000
@@ -347,7 +347,14 @@
 	struct apm_softc *sc;
 	struct apmregs *regs;
 {
+	extern int get_L2_size(void);
 	apm_resumes = APM_RESUME_HOLDOFF;
+
+#ifdef TP240
+	if (!(rdmsr(0x2ff) & 0x800))
+	    printf("apm_resume: CPU supports MTRRs but not enabled\n");
+	printf("apm_resume: %dKB L2 cache\n", get_L2_size());
+#endif
 
 	/* they say that some machines may require reinitializing the clock */
 	initrtclock();
Index: arch/i386/i386/locore.s
===================================================================
RCS file: /u/open/cvs/src/sys/arch/i386/i386/locore.s,v
retrieving revision 1.68
diff -u -r1.68 locore.s
--- arch/i386/i386/locore.s	9 Jan 2003 22:27:09 -0000	1.68
+++ arch/i386/i386/locore.s	23 Jun 2004 17:02:31 -0000
@@ -2025,3 +2025,46 @@
 
 	popl	%edi
 	ret
+
+#ifdef TP240
+.data
+	.align 2,0x90
+_intel_cachetable.3:
+	.long 0
+	.long 128
+	.long 256
+	.long 512
+	.long 1024
+	.long 2048
+.text
+	.align 2,0x90
+.globl _get_L2_size
+_get_L2_size:
+	pushl %ebp
+	movl %esp,%ebp
+	mov %cr0, %eax			/* turn on L2 cache */
+	and $0x9fffffff,%eax
+	mov %eax, %cr0
+	movl $2,%eax			/* inquire size of L2 cache */
+	cpuid
+	movl %edx,%eax
+	andl $255,%eax
+	cmpl $63,%eax
+	jle L4
+	cmpl $69,%eax
+	jg L4
+	leal -64(%eax),%edx
+	leal 0(,%edx,4),%eax
+	movl $_intel_cachetable.3,%edx
+	movl (%eax,%edx),%ecx
+	movl %ecx,%eax
+	jmp L2
+	.align 2,0x90
+L4:
+	movl $-1,%eax
+	jmp L2
+	.align 2,0x90
+L2:
+	leave
+	ret
+#endif